View MCM6323AYJ10_44143.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM6323A/D
Product Preview
MCM6323A
64K x 16 Bit 3.3 V Asynchronous Fast Static RAM
The MCM6323A is a 1,048,576 bit static random access memory organized as 65,536 words of 16 bits. Static design eliminates the need for external clocks or timing strobes; CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6323A is equipped with chip enable (E), write enable (W), and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems. Separate byte enable controls (LB and UB) allow individual bytes to be written and read. LB controls the 8 DQa bits, while UB controls the 8 DQb bits. The MCM6323A is available in a 400 mil small-outline J-leaded (SOJ) package and a 44-lead TSOP Type II package in copper leadframe for optimum printed circuit board (PCB) reliability. * * * * * * * * Single 3.3 V 0.3 V Power Supply Fast Access Time: 10, 12, 15 ns Equal Address and Chip Enable Access Time All Inputs and Outputs are TTL Compatible Data Byte Control Fully Static Operation Power Operation: 140/135/130 mA Maximum, Active AC Industrial Temperature Option: - 40 to + 85C Part Number: SCM6323AYJ10A BLOCK DIAGRAM
G OUTPUT ENABLE BUFFER 7 ADDRESS BUFFERS 9 ROW COLUMN DECODER DECODER 8 HIGH BYTE OUTPUT ENABLE LOW BYTE OUTPUT ENABLE 8 HIGH BYTE OUTPUT BUFFER HIGH BYTE WRITE DRIVER 8 DQb 8 YJ PACKAGE 400 MIL SOJ CASE 919-01 TS PACKAGE 44-LEAD TSOP TYPE II CASE 924A-01
PIN ASSIGNMENT
A A A A A E DQa DQa DQa DQa VDD VSS DQa DQa DQa DQa W A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A A A G UB LB DQb DQb DQb DQb VSS VDD DQb DQb DQb DQb NC A A A A NC
A 16
E
CHIP ENABLE BUFFER 64K x 16 BIT MEMORY ARRAY 16 SENSE AMPS 8
8
A A NC
W
WRITE ENABLE BUFFER
LOW BYTE OUTPUT BUFFER 8 LOW BYTE WRITE DRIVER
8 DQa 8
PIN NAMES
A . . . . . . . . . . . . . . . . . . . . . . . . Address Input E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable W . . . . . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . . . . Output Enable UB . . . . . . . . . . . . . . . . . . . . . . . . Upper Byte LB . . . . . . . . . . . . . . . . . . . . . . . . . Lower Byte DQa . . . . . . . . . . . . Lower Data Input/Output DQb . . . . . . . . . . . . Upper Data Input/Output VDD . . . . . . . . . . . . . . + 3.3 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . . . . . No Connection
8
LB UB
BYTE ENABLE BUFFER
HIGH BYTE WRITE ENABLE LOW BYTE WRITE ENABLE
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. REV 1 10/17/97
(c) Motorola, Inc. 1997 MOTOROLA FAST SRAM
MCM6323A 1
TRUTH TABLE (X = Don't Care)
E H L L L L L L L L G X H X L L L X X X W X H X H H H L L L LB X X H L H L L H L UB X X H H L L H L L Mode Not Selected Output Disabled Output Disabled Low Byte Read High Byte Read Word Read Low Byte Write High Byte Write Word Write VDD Current ISB1, ISB2 IDDA IDDA IDDA IDDA IDDA IDDA IDDA IDDA DQa's High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din DQb's High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din
ABSOLUTE MAXIMUM RATINGS (See Notes)
Rating Supply Voltage Voltage on Any Pin Output Current per Pin Package Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature Commerial Industrial Commerial Industrial Symbol VDD Vin Iout PD Tbias TA Tstg Value - 0.5 to + 4.6 - 0.5 to VDD + 0.5 20 .75 - 10 to + 85 - 45 to + 90 0 to + 70 - 40 to + 85 - 55 to + 150 Unit V V mA W C C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high-impedance circuits. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. All voltages are referenced to VSS. 3. Power dissipation capability will be dependent upon package characteristics and use environment.
MCM6323A 2
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V 0.3 V, TA = 0 to 70C, Unless Otherwise Noted) (TA = - 40 to + 85C for Industrial Temperature Offering) RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VDD VIH VIL Min 3.0 2.2 - 0.5* Typ 3.3 -- -- Max 3.6 VDD + 0.3** 0.8 Unit V V V
* VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20 ns) for I 20.0 mA. ** VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width 20 ns) for I 20.0 mA.
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VDD) Output Leakage Current (E = VIH, Vout = 0 to VDD) Output Low Voltage Output High Voltage (IOL = + 4.0 mA) (IOL = + 100 A) (IOH = - 4.0 mA) (IOH = - 100 A) Symbol Ilkg(I) Ilkg(O) VOL VOH Min -- -- -- 2.4 VDD - 0.2 Max 1.0 1.0 0.4 VSS + 0.2 -- Unit A A V V
POWER SUPPLY CURRENTS (See Note 1)
Parameter AC Active Supply Current (Iout = 0 mA) (VDD = max, f = fmax) AC Standby Current (E = VIH, VDD = max, f = fmax) CMOS Standby Current (VDD = max, f = 0 MHz, E VDD - 0.2 V, Vin VSS + 0.2 V, or VDD - 0.2 V) Commerical Industrial Commerical Industrial Commerical Industrial Symbol IDDA ISB1 ISB2 6323A-10 140 150 40 45 5 5 6323A-12 135 140 35 40 5 5 6323A-15 130 135 30 35 5 5 Unit mA mA mA Notes 2 2
NOTES: 1. Typical current = 25C @ 3.3 V. 2. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V, VIL = 0 V).
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Address Input Capacitance Control Input Capacitance Input/Output Capacitance Symbol Cin Cin CI/O Typ -- -- -- Max 6 6 8 Unit pF pF pF
MOTOROLA FAST SRAM
MCM6323A 3
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V 0.3 V, TA = 0 to +70C, Unless Otherwise Noted) (TA = - 40 to + 85C for Industrial Temperature Offering)
Logic Input Timing Measurement Reference Level . . . . . . . . 1.50 V Logic Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.50 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
READ CYCLE TIMING (See Notes 1, 2, 3, and 4)
MCM6323A-10 Parameter P Read Cycle Time Address Access Time Enable Access Time Output Enable Access Time Output Hold from Address Change Enable Low to Output Active Output Enable Low to Output Active Enable High to Output High-Z Output Enable High to Output High-Z Byte Enable Access Time Byte Enable Low to Output Active Byte High to Output High-Z Symbol S bl tAVAV tAVQV tELQV tGLQV tAXQX tELQX tGLQX tEHQZ tGHQZ tBLQV tBLQX tBHQZ Min 10 -- -- -- 3 3 0 -- -- -- 0 0 Max -- 10 10 4 -- -- -- 4 4 4 -- 5 MCM6323A-12 Min 12 -- -- -- 3 3 0 -- -- -- 0 0 Max -- 12 12 5 -- -- -- 5 5 5 -- 5 MCM6323A-15 Min 15 -- -- -- 3 3 0 -- -- -- 0 0 Max -- 15 15 6 -- -- -- 6 6 6 -- 5 Unit Ui ns ns ns ns ns ns ns ns ns ns ns ns 6, 7, 8 6, 7, 8 6, 7, 8 6, 7, 8 6, 7, 8 6, 7, 8 6 Notes N 5
NOTES: 1. W is high for read cycle. 2. For common I/O applications, minimization, or elimination of bus contention conditions is necessary during read and write cycles. 3. Device is continuously selected (E = VIL, G = VIL, and LB and/or UB = VIL). 4. Addresses valid prior to or coincident with E going low. 5. All read cycle timings are referenced from the last valid address to the first transitioning address. 6. Transition is measured 200 mV from steady-state voltage. 7. At any given voltage and temperature, tEHQZ (max) < tELQX (min), and tGHQZ (max) < tGLQX (min), both for a given device and from device to device. 8. This parameter is sampled and not 100% tested.
MCM6323A 4
MOTOROLA FAST SRAM
OUTPUT Z0 = 50 RL = 50 1.5 V 30 pF
Figure 1. Equivalent AC Test Load
2.0
1.5 DELTA TIME DELAY (ns)
1.0
OUTPUT CL
0.5 0
- 0.5
0
20
40
60
80
100
LUMPED CAPACITANCE, CL (pF) @ T = 25C, VDD = 3.3 V
Figure 2. Lumped Capacitive Load and Typical Derating Curve
DELTA TIME DELAY (ns)
+0.2 +0.1 0 -0.1 -0.2 - 0.3 3.0 3.1 3.2 3.3 3.4 3.5 3.6 OUTPUT
DELTA TIME DELAY (ns)
+0.3
+0.3 +0.2 +0.1 0 -0.1 - 0.2
-50 30 pF
-25
0
25
50
75
100
VDD (V) @ T = 25C
T (C) @ VDD = 3.3 V
Figure 3. Derating Across Temperature and Voltage
MOTOROLA FAST SRAM
MCM6323A 5
READ CYCLE 1 (See Note 7)
tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID
READ CYCLE 2 (See Note 8)
tAVAV A (ADDRESS) tAVQV tELQV E (CHIP ENABLE) tEHQZ tELQX G (OUTPUT ENABLE) tGLQV tGLQX LB, UB (BYTE ENABLE) tBLQV tBLQX Q (DATA OUT) DATA VALID tBHQZ tGHQZ
MCM6323A 6
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6323A-10 Parameter P Write Cycle Time Address Setup Time Address Valid to End of Write Write Pulse Width Byte Pulse Width Data Valid to End of Write Data Hold Time Write Low to Data High-Z Write High to Output Active Write Recovery Time Symbol S bl tAVAV tAVWL tAVWH tWLWH, tWLEH tBLWH, tBLEH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 10 0 8 8 8 4 0 0 3 0 Max -- -- -- -- -- -- -- 4 -- -- MCM6323A-12 Min 12 0 9 9 9 5 0 0 3 0 Max -- -- -- -- -- -- -- 5 -- -- MCM6323A-15 Min 15 0 10 10 10 6 0 0 3 0 Max -- -- -- -- -- -- -- 6 -- -- Unit Ui ns ns ns ns ns ns ns ns ns ns 4, 5, 6 4, 5, 6 Notes N 3
NOTES: 1. A write occurs during the overlap of E low, W low, and LB and/or UB low. 2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles. 3. All write cycle timings are referenced from the last valid address to the first transitioning address. 4. Transition is measured 200 mV from steady-state voltage. 5. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device. 6. This parameter is sampled and not 100% tested.
WRITE CYCLE 1
(W Controlled) tAVAV A (ADDRESS) tAVWH E (CHIP ENABLE) tWLEH tWLWH W (WRITE ENABLE) tAVWL LB, UB (BYTE ENABLE) tDVWH D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z tWHQX DATA VALID tBLEH tBLWH tWHDX tWHAX
MOTOROLA FAST SRAM
MCM6323A 7
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MCM6323A-10 Parameter P Write Cycle Time Address Setup Time Address Valid to End of Write Enable to End of Write Data Valid to End of Write Data Hold Time Write Recovery Time Symbol S bl tAVAV tAVEL tAVEH tELEH, tELWH tDVEH tEHDX tEHAX Min 10 0 8 8 4 0 0 Max -- -- -- -- -- -- -- MCM6323A-12 Min 12 0 9 9 5 0 0 Max -- -- -- -- -- -- -- MCM6323A-15 Min 15 0 10 10 6 0 0 Max -- -- -- -- -- -- -- Unit Ui ns ns ns ns ns ns ns 4, 5 Notes N 3
NOTES: 1. A write occurs during the overlap of E low, W low, and LB and/or UB low. 2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles. 3. All write cycle timings are referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition. 5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
(E Controlled) tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL W (WRITE ENABLE) tELWH tEHAX
LB, UB (BYTE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX
Q (DATA OUT)
HIGH-Z
MCM6323A 8
MOTOROLA FAST SRAM
WRITE CYCLE 3 (B Controlled, See Notes 1 and 2)
MCM6323A-10 Parameter P Write Cycle Time Address Setup Time Address Valid to End of Write Write Pulse Width Byte Pulse Width Symbol S bl tAVAV tAVBL tAVBH tWLWH, tWLEH tBLWH, tBLEH, tBLBH tDVBH tBHDX tWLQZ tWHQX tBHAX Min 10 0 8 8 8 Max -- -- -- -- -- MCM6323A-12 Min 12 0 9 9 9 Max -- -- -- -- -- MCM6323A-15 Min 15 0 10 10 10 Max -- -- -- -- -- Unit Ui ns ns ns ns ns Notes N 3
Data Valid to End of Write Data Hold Time Write Low to Data High-Z Write High to Output Active Write Recovery Time
5 0 0 3 0
-- -- 4 -- --
6 0 0 3 0
-- -- 5 -- --
7 0 0 3 0
-- -- 6 -- --
ns ns ns ns ns 4, 5, 6 4, 5, 6
NOTES: 1. A write occurs during the overlap of E low, W low, and LB and/or UB low. 2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles. 3. All write cycle timings are referenced from the last valid address to the first transitioning address. 4. Transition is measured 200 mV from steady-state voltage. 5. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device. 6. This parameter is sampled and not 100% tested.
WRITE CYCLE 3
(B Controlled) tAVAV A (ADDRESS) tAVBH E (CHIP ENABLE) tAVBL LB, UB (BYTE ENABLE) tBLEH tBLWH tBLBH tWLEH tWLWH W (WRITE ENABLE) tDVBH D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z tWHQX DATA VALID tBHDX tBHAX
MOTOROLA FAST SRAM
MCM6323A 9
ORDERING INFORMATION
(Order by Full Part Number) MCM 6323A YJ
Motorola Memory Prefix Part Number
XX
X
X
Shipping Method (R = Tape and Reel, Blank = Rails for SOJ, Blank = Trays for TSOP) Temperature (Blank = Commercial, A = Industrial) Speed (10 = 10 ns, 12 = 12 ns, 15 = 15 ns) Package (YJ = 400 mil SOJ, TS = 44-Lead TSOP Type II)
Full Commercial Part Numbers -- MCM6323AYJ10 MCM6323AYJ10R MCM6323ATS10 MCM6323ATS10R Full Industrial Part Numbers -- SCM6323AYJ10A SCM6323AYJ10AR SCM6323ATS10A SCM6323ATS10AR
MCM6323AYJ12 MCM6323AYJ12R MCM6323ATS12 MCM6323ATS12R SCM6323AYJ12A SCM6323AYJ12AR SCM6323ATS12A SCM6323ATS12AR
MCM6323AYJ15 MCM6323AYJ15R MCM6323ATS15 MCM6323ATS15R SCM6323AYJ15A SCM6323AYJ15AR SCM6323ATS15A SCM6323ATS15AR
MCM6323A 10
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
YJ PACKAGE 400 MIL SOJ CASE 919-01
44 23 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, TIE BAR BURRS AND GATE BURRS. MOLD FLASH, TIE BAR BURRS AND GATE BURRS SHALL NOT EXCEED 0.006 PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010 PER SIDE. 4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS D AND E1 AND, HENCE, DATUMS A AND B, ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 5. DIMENSION b1 DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE SHOULDER WIDTH TO EXCEED b1 MAX BY MORE THAN 0.005. THE DAMBAR INTRUSION(S) SHALL NOT REDUCE THE SHOULDER WIDTH TO LESS THAN 0.001 BELOW b1 MIN. INCHES MIN MAX 0.128 0.148 0.025 --- 0.082 --- 0.035 0.045 0.015 0.020 0.026 0.032 1.120 1.130 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC 0.030 0.040
E1
1
22
B A D
44X b1 42X
e
0.007
L
CAB A
A3
SEATING PLANE
e /2 C
44X
A 0.004 C
b
M
0.007
CAB
DIM A A1 A2 A3 b b1 D E E1 E2 e R1
E A A2
44X R
0.007
M
CAB
R1
A1 0.015 B
22 ZONES 2X
E2 /2 E2 VIEW A-A
MOTOROLA FAST SRAM
MCM6323A 11
TS PACKAGE 44-LEAD TSOP TYPE II CASE 924A-01 VIEW A
3 R R
B
4 4 2
(R1) (R2)
A1 E1 AA L DETAIL A ROTATED 90 _ CLOCKWISE b1
1 22
q
A A 0 A2 .
22X E 0M C0 A 8
BASE METAL
(
0
.
c1 2
44X
0.004 (0.1) C
SEATING PLANE 4X
e /2
42X
e
C
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.006 (0.015) PER SIDE. 4. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSIONS SHALL NOT ALLOW THE b DIMENSION TO EXCEED 0.023 (0.58). INCHES MILLIMETERS MIN MAX MIN MAX --- 0.050 --- 1.270 0.002 0.006 0.051 0.152 0.038 0.042 0.965 1.067 0.012 0.018 0.305 0.457 0.012 0.016 0.305 0.406 0.005 0.008 0.127 0.203 0.004 0.006 0.101 0.152 0.721 0.729 18.313 18.517 0.0315 BSC 0.800 BSC 0.456 0.470 11.582 11.938 0.396 0.404 10.058 10.262 0.016 0.023 0.406 0.584 0.004 REF 0.100 REF 0.004 REF 0.100 REF 0_ 5_ 0_ 5_
DIM A A1 A2 b b1 c c1 D1 e E E1 L R1 R2
q
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.; SPD, Strategic Planning Office; 4-32-1, Nishi-Gotanda; Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488
MfaxTM : RMFAX0@email.sps.mot.com - TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, Motorola Fax Back System - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 - http://sps.motorola.com /mfax / HOME PAGE : http://motorola.com/sps / CUSTOMER FOCUS CENTER: 1-800-521-6274
MCM6323A 12
EEEE CCCC EEEE CCCC EEEE
) b 0.008 (0.2)
M
D1
c
TZ
SECTION A-A
40 PLACES
MCM6323A/D MOTOROLA FAST SRAM

▲Up To Search▲

Price & Availability of MCM6323AYJ10

	To Download MCM6323AYJ10 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .